In, for example, a high-speed interface transmitting a stream of bits with a source-synchronous clock, it is common to perform serialization/deserialization in order to process the bit stream at a lower clock frequency. An example of such a system is depicted in FIG. 1. The serializer 11a in the transmitter 11 may perform serialization, where serializer 11a may take words of size N-bits per word at a rate of M words per second (which may, e.g., be stored in a FIFO buffer 11b prior to serialization) and send them out over a channel to a receiver 12 at a rate of M×N bits per second. The receiver 12 may then receive the bit stream and perform deserialization 12a to convert it back into words of size N-bits per word at the rate of M words per second (which may be stored, e.g., in a FIFO buffer 12b after deserialization). A system such as the one shown in FIG. 1 may include a source-synchronous clock (i.e., a clock sent from the same source as the data), which may be sent in-phase with the data from the transmitter 11 to the receiver 12.
However, a number of problems are possible that may result in mismatches between the data and the received clock. For example, board-level trace mismatches between different data channels, trace mismatches between data and clock, voltage/temperature differences, and process variations may all lead to differences in the arrival times of the clock and data at the input of a sampling receiver. For a system that transmits several data bits (e.g., data channels) with a single clock, the situation may be worse because each data channel may have a different skew with respect to the single clock, and this may further complicate the sampling of all the data channels using the same clock; an example of this is shown in FIG. 2. The skew between data channels could be so severe that there is no common window for sampling all data channels; an example of such a scenario is shown in FIG. 3, in which Data Channels 1, 2 and 3 may be such that, for example, any location where one may locate a sampling clock would result in data from different words being sampled. For example, if the sampling is performed at a time corresponding to line 31, the correct data may be obtained for Data Channel 1 and Data Channel 3, but not for Data Channel 2 (the sampling time may be too early). Similarly, if the sampling is performed at a time corresponding to line 32, correct data may be obtained for Data Channel 2 and Data Channel 3, but not for Data Channel 1 (the sampling time may be too late).
A possible solution to this problem is to use a technique called, “dynamic phase alignment.” While some dynamic phase alignment techniques have been proposed and/or implemented, e.g., by Altera Corporation and Xilinx, Inc., such techniques may have drawbacks. For example, some may use specialized components that may not be readily available and/or easily fabricated, some may require relatively large amounts of space on a chip to implement, and some may need a relatively large period of time to achieve phase alignment.